
Options

1. Logicvision Embedded core test

   Advantages:
   - Fully supported automated tool flow.

   Disadvantages:
   - Costs way too much, not enough licenses per chip.

2. Home-built PRPG/MISR 

  Description:
   Logicvision used to construct top-level with logicbist and
   TAP controllers.  Each core is stitched and then wrapped with
   a home-built "p1500" wrapper that includes a home-built 
   logicbist controller.  Software is used to generate vectors
   for fault-simulation (within the logicvision tools). The
   expected output vectors from LV is used by more software to 
   calculate the expected signature for the MISR portion of 
   the design.

  Advantages:
    - Get the hierarchical bist without paying for LV's.
    - Total control over the design, whether done by automated tool 
      or not.
    - Offer the choice of programmable polynomials and signatures, with 
      a default polynomial/signature pair for power-on self-test.
    - Predictable interface to the BIST controller.
    - Can use existing LBIST controller for top-level logic and 
      interconnect BIST.

  Disadvantages:
    - Can't use LV to generate verilog testbenches and WGL for 
      core logic-bist.
    - Have to write tools to generate vectors for input to LV's fault 
      simulation for the core.
    - Have to write tools to generate testbenches for verilog and WGL.
    - Shared-isolation ring (used for core isolation) is not available 
      in the standard release of the LV tools; Only available with the
      embedded core test version.
    - Have to hand-stitch up each core isolation ring, if shared isolation is
      required; Could use home-grown tools for this, or just make requirements
      of designers to do so ahead of time.
    
3. Shared LBIST controller 

    Description:
    Use the top-level logicbist controller to run logicbist against
    individual cores one at a time, and then run interconnect bist against
    the top-level interconnect and logic.

    Advantages:
    - Can use the LV tool suite to generate all test patterns and testbenches.

    Disadvantages:
    - Requires hand-tuning of clocks and paths to/from the logicbist controller.
    - Requires clock architecture that LV tools may not like, and may not be 
      automatically closable in timing-driven layout.
    - Requires flops floating at top-level for pipelining control and data lines
      between the global bist controller and each core.
    - Requires hacking up the netlist (to remove all cores except the one under
      test, or all cores in the case of top-level interconnect testing) to 
      generate test vectors.  



